[News Article] SK hynix exec pins high hopes on new US packaging plant
SK hynix exec pins
high hopes on new US packaging plant
By
Jie Ye-eun, The Korea Herald - With the advances in artificial intelligence,
there is a growing demand for cutting-edge memory chips. As the technology
environment has evolved, SK hynix vice president expressed his ambition to
contribute to the development of the highest-performance memory products
through advanced packaging technologies. “Package
and test (P&T) technology is turning into a crucial factor in the battle
for semiconductor leadership,” Choi Woo-jin, vice president in charge of SK
hynix’s package and test division said in an interview posted on the chip
maker’s blog on Thursday. Choi
is a packaging expert who has conducted and led research and development in
chip memory packaging over the past three decades. The P&T division that he
oversees takes care of the back-end process where wafers are packaged into
products and tested to ensure they meet customer requirements. Semiconductor
packaging has become a pivotal technology for high bandwidth memory (HBM), a
critical chip to generative AI tools. While packaging traditionally held the
role of electrically connecting chips and protecting them from external shocks,
it is vital to enabling differentiated product performances, he added. Choi
stressed the chip maker’s commitment to driving endless innovation and
leveraging its technological prowess to the fullest. “In the age of AI, SK
hynix is focusing on signature memories which possess diverse aspects required
by customers, including various capabilities, sizes, shapes and power
efficiency,” he added. The
vice president also highlighted SK hynix’s swift response to the surge in
demand for DRAMs with the emergence of generative AI, such as ChatGPT, which
involved the speedy adoption of through-silicon via (TSV) packaging lines to
enhance production capacity without additional investment. By
advancing its proprietary technologies, such as TSV and mass reflow-molded
underfill (MR-MUF), the chip maker has been able to enhance HBM performance.
The vice president further hinted that the company is working on developing
various next-generation packaging technologies, including chiplet4 and hybrid
bonding. So
far, the TSV technology can reduce the thickness of a single DRAM chip by 40
percent and achieve the same stack height level as the 16-gigabyte product. The
MR-MUF technology can place multiple chips on the lower substrate and bond them
at once through reflow, and then simultaneously fill the gap between the chips
with a mold material. While
SK hynix announced that will invest about $3.87 billion to build an advanced
chip packing fabrication and R&D facility in Indiana, Choi has played a key
role in this process by planning the strategy for the construction and
operations of the fab. "Once
the factory is fully operational, we expect it to make a significant
contribution to strengthening the company’s AI memory technology and business
leadership," he said. "In
the short term, we plan to strengthen our domestic production capabilities to
meet the demand for HBM while leveraging our global base to maximize
profitability. ... In the long run, we aim to secure more innovative packaging
technologies like MR-MUF, which is now a vital technology to HBM.” Source:
https://www.koreaherald.com/view.php?ud=20240411050592
2024.04.12
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